1. Field
The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display which can reduce the number of output channels of a data driving circuit and a driving method thereof.
2. Description of the Related Art
A liquid crystal display displays an image by adjusting the light transmittance of liquid crystal using an electric field. Such a liquid crystal display comprises a liquid crystal display panel having liquid crystal cells arranged in a matrix form and driving circuits for driving the liquid crystal cells.
On the liquid crystal display panel, as shown in FIG. 1, a gate line GL and a data line DL cross each other, and a thin film transistor (hereinafter, referred to as “TFT”) for driving the liquid crystal cell Clc is formed at a crossing of the gate line GL and the data line GL. The TFT supplies a data voltage Vd supplied via the data line DL to a pixel electrode Ep of the liquid crystal cell Clc in response to a scan pulse supplied via the gate line GL. To this end, a gate electrode of the TFT is connected to the gate line GL, a source electrode thereof is connected to the data line DL, and a drain electrode thereof is connected to the pixel electrode Ep of the liquid crystal cell Clc. The liquid crystal cell Clc displays gray levels by a potential difference between the data voltage Vd supplied to the pixel electrode Ep and a common voltage Vcom supplied to a common electrode Ec. The common electrode Ec is formed at an upper glass substrate or a lower glass substrate of the liquid crystal display panel depending upon a method of applying an electric field to the liquid crystal cell Clc. A storage capacitor Cst is formed between the common electrode Ec and the pixel electrode Ep of the liquid crystal cell Clc to maintain a voltage charged in the liquid crystal cell Clc.
The driving circuit board comprises a data driving circuit for converting digital video data into analog video data voltages and supplying the analog video data voltages to the data lines of the liquid crystal display panel. Typically, as shown in FIG. 2, output channels S1 to S9 of the data driving circuit 10 are connected one to one to the data lines D1 to D9 formed on the liquid crystal display panel 20. The data driving circuit 10 is typically more expensive than other parts. Therefore, attempts have been made continuously to reduce the number of output channels of the data driving circuit 10 by connecting the output channels of the data driving circuit to the data lines at a ratio of 1:2, 1:3, 1:4, 1:5, or lower.
FIG. 3 shows an example in which output channels S1, S2, and S3 of the data driving circuit 10 are connected to the data lines D1 to D9 at a ratio of 1:3 through a conventional sampling switching circuit 30. The sampling switching circuit 30 time-divides a data voltage output through an output channel and distributes the time-divided data voltage to three data lines. The time division operation in the sampling switching circuit 30 is performed by DEMUX switches MT1, MT2, and MT3 which are sequentially turned on by DEMUX control signals DM1, DM2, and DM3.
The DEMUX control signals DM1, DM2, and DM3 are generated such that they are sequential within 1 horizontal period 1H and do not overlap with each other. A generation cycle of the DEMUX control signals DM1, DM2, and DM3 is set to about 1 horizontal period 1H. In FIG. 4, ‘Hsync’ indicates a horizontal synchronization signal, ‘(1)’ indicates an interval between scan pulses applied to neighboring gate lines, ‘(2)’ and ‘(5)’ indicate an interval between a scan pulse and a DEMUX control signal, ‘(3)’ indicates a pulse width of a DEMUX control signal (corresponding to a turn-on period of the DEMUX switches), and ‘(4)’ indicates an interval between neighboring DEMUX control signals.
The conventional driving method has the following problem because the DEMUX controls signals are generated in the same cycle (interval of 1H).
In accordance with the conventional driving method, the higher the resolution of the liquid crystal display panel and the higher the distribution ratio, the more difficult it is to ensure a timing margin for the DEMUX control signals. Especially, unless the interval of ‘(4)’ of FIG. 4 is ensured, data voltages, which have to be temporally divided and supplied, are mixed with each other and therefore an unwanted charging result is produced. The reason why it is difficult to ensure a timing margin is because the width of 1 horizontal period 1H decreases depending on the resolution of the liquid crystal display panel and the distribution ratio as in the following Table 1.
TABLE 1DEMUX switchturn-on time [usec]1 H1:21:31:6VerticalHorizontaltimedistri-distri-distri-ResolutionResolution[usec]butionbutionbutionVGA48064024.5110.756.843.21WVGA48080019.848.425.282.43qHD54096016.676.834.221.90WSVGA600102415.666.333.891.74WXGA768128012.634.812.881.23WSXGA+105016809.693.341.900.74HD1080108019208.502.751.500.54
Also, the higher the resolution of the liquid crystal display panel, the narrower the width of 1 horizontal period 1H. Therefore, the driving frequency of the DEMUX switches which are turned on every 1 horizontal period 1H, that is, the frequency of the DEMUX control signals, increases. As the frequency fDeMUX of the DEMUX control signals increases, the power consumption PDeMUX of the sampling switching circuit increases as in the following Equation 1:PDeMUX=Cdm×VDeMUX2×fDeMUX,  Equation 1
here, fDeMUX=fFrame×HTotal 
wherein ‘fFrame’ indicates frame frequency, ‘HTotal’ indicates the number of horizontal lines of the liquid crystal display panel, ‘Cdm’ indicates the parasitic capacitance of signal lines for supplying the DEMUX control signals DM1 to DM3, as shown in FIG. 5, and ‘VDeMUX’ indicates the swing width of the DEMUX control signals. In FIG. 5, ‘Rdm’ denotes the line resistance of the signal lines for supplying the DEMUX control signals DM1 to DM3.